Open AccessHigh-level Synthesis Integrated Verification
Author(s) -
Michael Dossis
Publication year - 2015
Publication title -
engineering, technology and applied science research/engineering, technology and applied science research
Language(s) - English
Resource type - Journals
eISSN - 2241-4487
pISSN - 1792-8036
DOI - 10.48084/etasr.596
Subject(s) - computer science , functional verification , intelligent verification , time to market , high level verification , high level synthesis , verification , formal verification , software verification , electronic system level design and verification , code (set theory) , software engineering , work (physics) , embedded system , computer architecture , programming language , software , engineering , set (abstract data type) , field programmable gate array , software development , software construction , mechanical engineering
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.