Open AccessHardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform
Author(s) -
Taoufik Saidani,
Refka Ghodhbani
Publication year - 2022
Publication title -
engineering, technology and applied science research/engineering, technology and applied science research
Language(s) - English
Resource type - Journals
eISSN - 2241-4487
pISSN - 1792-8036
DOI - 10.48084/etasr.4615
Subject(s) - field programmable gate array , computer science , vhdl , embedded system , frame rate , enhanced data rates for gsm evolution , hardware acceleration , computer hardware , frame (networking) , design flow , video processing , system on a chip , artificial intelligence , telecommunications
The study conducted in the current paper consists of validating an original design flow for the rapid prototyping of real-time image and video processing applications on FPGAs. A video application for edge detection with Simulink HDL coder and Vivado High-Level Synthesis (HLS) has been designed as if the code was going to be executed on a conventional processor. The developed tools will automatically translate the code into VHDL hardware language using an advanced compilation technique. This amounts to embedding processors on Xilinx Zynq-7000 System on-Chip (SoC) device in an optimal manner. This automated hardware design flow reduces the time to create a prototype since only the high-level description is required. The design of the video edge detection system is implemented on Xilinx Zynq-7000 platform. The result of the implementation gave effective resource utilization and a good frame rate (95 FPS) under 170MHz frequency.