Open AccessC-Pack: Cache Compression for Microprocessor Performance
Author(s) -
T. Narasimhulu
Publication year - 2011
Publication title -
international journal of power system operation and energy management
Language(s) - English
Resource type - Journals
ISSN - 2231-4407
DOI - 10.47893/ijpsoem.2011.1019
Subject(s) - lossless compression , computer science , cache , compression ratio , microprocessor , data compression , computer hardware , parallel computing , cpu cache , compression (physics) , cache pollution , data compression ratio , embedded system , cache algorithms , computer engineering , image compression , algorithm , artificial intelligence , engineering , materials science , composite material , image (mathematics) , automotive engineering , image processing , internal combustion engine
Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, mostpast work, and all work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. In this work, I present a lossless compression algorithm that has been designed for fast on-line data compression, and cache compression in particular. The algorithm has a number of novel features tailored for thisapplication, including combining pairs of compressed lines into one cache line and allowing parallel compression of multiple words while using a single dictionary and without degradation in compression ratio. We reduced the proposed algorithm to aregister transfer level hardware design, permitting performance, power consumption, and area estimation.