Open AccessDECOUPLING LOGIC BASED SRAM DESIGN FOR POWER REDUCTION IN FUTURE MEMORIES
Author(s) -
M. Premkumar,
Ch. Jaya Prakash
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1207
Subject(s) - decoupling (probability) , static random access memory , reduction (mathematics) , computer science , column (typography) , power (physics) , electronic engineering , embedded system , computer hardware , engineering , control engineering , mathematics , telecommunications , physics , geometry , quantum mechanics , frame (networking)
In this paper we are going to modify the column decoupled SRAM for the purpose of more reduced leakages than the existing type of designs as well as the new design which is combined of virtual grounding with column decoupling logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area & power factors the simulations were done using microwind & DSCH results