Open AccessCRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN
Author(s) -
K. Sanjeevarao,
A. Ramkumar
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1206
Subject(s) - computer science , multiplier (economics) , arithmetic , adder , algorithm , binary number , very large scale integration , booth's multiplication algorithm , encoding (memory) , computer hardware , power of two , parallel computing , latency (audio) , mathematics , embedded system , telecommunications , artificial intelligence , economics , macroeconomics
With the advent of the VLSI technology, designers could design simple chips with the more number of transistors. multipliers have large area, long latency and consume considerable power. Reduction of power consumption makes a device reliable. and The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition, a high-radix-modified booth encoding algorithm is desired. However its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary(NB) to RB conversion. This paper proposes new RB booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent booth encoded digits to directly from an RB partial product to avoid the hard multiple of high-radix booth encoding without incurring any correction vector, and the algorithm achieved high speed compared to existing multiplication algorithms for a gamut of power –of-to word lengths up to 64 b.