Open AccessDESIGN AND IMPLEMENTATION OF TURBO CODER FOR LTE ON FPGA
Author(s) -
Santosh Gooru,
S. Rajaram
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1196
Subject(s) - turbo code , turbo equalizer , computer science , noisy channel coding theorem , turbo , encoder , field programmable gate array , serial concatenated convolutional codes , encoding (memory) , wimax , computer engineering , decoding methods , soft decision decoder , algorithm , computer hardware , wireless , low density parity check code , concatenated error correction code , telecommunications , block code , engineering , error floor , artificial intelligence , automotive engineering , operating system
Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH and HSPA incorporates turbo code for its excellent performance. This work provides an overview of the novel class of channel codes referred to as turbo codes, which have been shown to be capable of performing close to the Shannon Limit. It starts with a brief discussion on turbo encoding, and then move on to describing the form of the iterative decoder most commonly used to decode turbo codes. Here, Turbo decoder uses original MAP algorithm instead of using the approximated Max log-MAP algorithm thereby it reduces the number iterations to decode the transmitted information bits. This paper presents the FPGA (Field Programmable Gate Array) implementation simulation results for Turbo encoder and decoder structure for 3GPP-LTE standard.