Open AccessA LAYERED DECODING ARCHITECTURE FOR LDPC DECODER WITH LOW ENERGY CONSUMPTION
Author(s) -
G. Sagar,
M. Sandeep Kumar
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1194
Subject(s) - decoding methods , computer science , low density parity check code , soft decision decoder , energy consumption , parallel computing , reduction (mathematics) , algorithm , computer hardware , mathematics , engineering , geometry , electrical engineering
Low-density parity-check (LDPC) decoder requires large amount of memory access which leads to high energy consumption. To reduce the energy consumption of the LDPC decoder, memory-bypassing scheme has been proposed for the layered decoding architecture which reduces the amount of access to the memory storing the soft posterior reliability values. In this work, we present a scheme that achieves the optimal reduction of memory access for the memory bypassing scheme. The amount of achievable memory bypassing depends on the decoding order of the layers. We formulate the problem of finding the optimal decoding order and propose algorithm to obtain the optimal solution. We also present the corresponding architecture which combines some of memory components and results in reduction of memory area. The proposed decoder was implemented in TSMC 0.18 m CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9–19.3% compared with the state-of-the-art design. At the same time, 95.6%–100% hardware utilization rate is achieved.