Open AccessSTDFF A PASS TRANSISTOR BASED FLIP FLOP DESIGN FOR EFFICIENT INTEGRATED CIRCUITS
Author(s) -
G. Lakshmi Praneetha,
P. Hareesh
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1181
Subject(s) - flip flop , transistor , computer science , electronic circuit , flops , transistor count , power (physics) , enhanced data rates for gsm evolution , electronic engineering , flip , emphasis (telecommunications) , electrical engineering , engineering , parallel computing , voltage , artificial intelligence , telecommunications , physics , apoptosis , biochemistry , chemistry , quantum mechanics
In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of DLDFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edge triggered flip-flop named as Switching Transistor based D Flip-Flop(STDFF) with reduced number of transistors which will reduce the overall power area as well as delay. The simulations are done using Microwind & DSCH analysis software tools and the result between all those types are listed below. Our proposed system simulations are done under 50nm technology and the results are tabulated below. In that our proposed system is showing better output than the other flip-flops compared here.