Open AccessDESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT
Author(s) -
S.A. Jyotsnamayee,
M. Murali Krishna
Publication year - 2014
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2014.1163
Subject(s) - capacitance , inverter , computer science , electronic engineering , arithmetic , electrical engineering , mathematics , engineering , physics , voltage , electrode , quantum mechanics
Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.. Conventional methods use repetitive manual testing guided by Logical Effort (LE).In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, using LE.The main objective of the paper is to calculate the delay using VerilogHDL and synthesized the output driven by it by increasing the speed using optimized paths.