Open AccessANALYZING THE PERFORMANCE OF CARRY TREE ADDERS BASED ON FPGA’S
Author(s) -
Renukuntla Kiran,
Sunitha Nampally
Publication year - 2013
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2013.1152
Subject(s) - adder , carry (investment) , computer science , carry save adder , field programmable gate array , parallel computing , overhead (engineering) , very large scale integration , arithmetic , computer hardware , mathematics , embedded system , telecommunications , finance , latency (audio) , economics , operating system
In this paper carry tree adders are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and delay measurements were made with a high-performance logic analyzer. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256.