Open AccessLDPC ARCHITECTURE IMPLEMENTATION BY REDUCING THE MEMORY UTILIZATION
Author(s) -
B. Doss,
M. Sailaja
Publication year - 2013
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2013.1126
Subject(s) - low density parity check code , computer science , parallel computing , coding (social sciences) , field programmable gate array , node (physics) , computation , algorithm , decoding methods , computer hardware , mathematics , engineering , statistics , structural engineering
As the low density parity check codes has proved their accuracy in error correcting .considering the ldpc as reference the architecture of ldpc is studied .ldpc coding contains check nodes and variable nodes which has their memory elements respectively .so an efficient use of memory can decrease the computation time. Further the arrays of memory requirement has been decreased by making the memory global to all the nodes . ldpc is considered as a finite state machine in which each node is a state .An efficient memory utilization method has been proposed to decrease the memory utilization in the fpga.