Open AccessNOVEL GROUND BOUNCE NOISE REDUCTION WITH ENHANCED POWER AND AREA EFFICIENCY FOR LOW POWER PORTABLE APPLICATION
Author(s) -
Mohd Abdul Sumer,
K. Tirumala Rao,
P. S. T. N. Srinivas
Publication year - 2013
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2013.1122
Subject(s) - ground bounce , noise immunity , adder , dissipation , electronic circuit , electronic engineering , noise reduction , noise (video) , electrical engineering , computer science , adiabatic process , logic gate , power (physics) , reduction (mathematics) , leakage (economics) , engineering , physics , acoustics , transistor , cmos , mathematics , voltage , artificial intelligence , gate dielectric , image (mathematics) , geometry , quantum mechanics , macroeconomics , thermodynamics , economics
As technology scales into the nanometer regime ground bounce noise and heat dissipation immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit PFAL full adder cells are proposed for mobile applications with low ground bounce noise and heat dissipation in the circuits using adiabatic logic. The simulations are done using DSCH &MicrowindSoftware.