Open AccessA VLSI DSP DESIGN AND IMPLEMENTATION OF ALL POLE LATTICE FILTER USING RETIMING METHODOLOGY
Author(s) -
Pranay Gupta,
Tarun Kumar Rawat
Publication year - 2012
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2012.1082
Subject(s) - retiming , lattice phase equaliser , very large scale integration , lattice (music) , computer science , clock rate , digital signal processing , clock signal , electronic engineering , timing failure , electronic circuit , adaptive filter , computer hardware , parallel computing , synchronous circuit , algorithm , embedded system , engineering , electrical engineering , chip , telecommunications , physics , acoustics
All pole lattice fil ters are used in a variety of signal processing applications that is speech processing, adaptive filters and various other applications. The implementation of lattice f i l t e r requires more clock period hence low speed. There are various transformation technique pr es ent for design of high-speed or low-area or lowpower implementations. This paper presents design of high-speed (smaller clock period) implementation of 8th order all pole lattice filter using the methodology named as Retiming. Retiming reduces the clock period of the circuit, reducing the number of registers in the circuit, reducing the power consumption of the circuit. Therefore, retiming has been used to reduce the clock period of all pole lattice filters and it increases the speed of the system.