Open AccessDESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH
Author(s) -
Channakka Lakkannavar,
Shrikanth K. Shirakol,
Kalmeshwar N. Hosur
Publication year - 2012
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2012.1065
Subject(s) - flash adc , comparator , analog to digital converter , successive approximation adc , computer science , cmos , electronic engineering , flash (photography) , analog signal , effective number of bits , converters , delta sigma modulation , computer hardware , 12 bit , integrating adc , digital to analog converter , amplifier , electrical engineering , voltage , engineering , digital signal processing , capacitor , art , visual arts , ćuk converter
Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.