Open AccessGenerating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm
Author(s) -
Ravikumar Balasubramanian,
K. Goutham,
S Jenitha,
R M Rahul,
Thirupathie Raja B,
Vijaya Kumar S
Publication year - 2011
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2011.1027
Subject(s) - combinational logic , very large scale integration , benchmark (surveying) , algorithm , electronic circuit , automatic test pattern generation , genetic algorithm , computer science , fault coverage , sequential logic , parallel computing , logic gate , engineering , embedded system , machine learning , electrical engineering , geodesy , geography
In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.