Open AccessDesign and Implementation of a Lossless Serial High-Speed Data Compression System
Author(s) -
J. Sunil Kumar,
Gaurav Kumar
Publication year - 2011
Publication title -
international journal of electronic signal and systems
Language(s) - English
Resource type - Journals
ISSN - 2231-5969
DOI - 10.47893/ijess.2011.1001
Subject(s) - lossless compression , computer science , uncompressed video , data compression , field programmable gate array , latency (audio) , computer hardware , data compression ratio , compression ratio , very large scale integration , throughput , lossy compression , embedded system , real time computing , image compression , video processing , engineering , telecommunications , algorithm , wireless , artificial intelligence , internal combustion engine , automotive engineering , video tracking , image (mathematics) , image processing
The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the X-Match algorithm. This design involves important trade off that affects the compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware. This device typical compression ratio that halves the original uncompressed data. This device is specifically targeted to enhance the performance of Gbits/s data networks and storage applications where it can double the performance of the original systems. To get high compression rate or to get high data rate of communication not restriction to follow the parallel architecture of data compression. By using existing method the main draw backs are 1. Variation in compression 2. Throughput, 3.Latency, 4.High space, 5. High power. So by using this proposed method we can reduce the variation in the compression, latency and increase through put. And this novel VLSI architecture has a power consumption of 81mwatts power