Open AccessDESIGN &ANALYSIS OF DUAL STACK METHOD FOR FUTURE TECHNOLOGIES
Author(s) -
P. Ravali Teja,
Deepak Kumar
Publication year - 2015
Publication title -
international journal of electrical and electronics engineering
Language(s) - English
Resource type - Journals
ISSN - 2231-5284
DOI - 10.47893/ijeee.2015.1163
Subject(s) - very large scale integration , computer science , power gating , electronic circuit , power analysis , power (physics) , leakage (economics) , dual (grammatical number) , leakage power , flops , electronic engineering , scaling , stack (abstract data type) , software , electrical engineering , embedded system , engineering , voltage , transistor , parallel computing , algorithm , cryptography , mathematics , art , programming language , physics , geometry , literature , quantum mechanics , economics , macroeconomics
As low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly so for removing these kind of leakages and to provide a better power efficiency we are using many types of power gating techniques. In this paper we are going to analyse the different types of flip-flops using different types of power gated circuits using low power VLSI design techniques and we are going to display the comparison results between different nanometer technologies. The NMOS1mulations were done using Microwind Layout Editor & DSCH software and the results were given below.