Open AccessIMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER
Author(s) -
Syam Kumar Nagendla,
K. Miranji
Publication year - 2015
Publication title -
international journal of electrical and electronics engineering
Language(s) - English
Resource type - Journals
ISSN - 2231-5284
DOI - 10.47893/ijeee.2015.1162
Subject(s) - adder , carry save adder , computer science , power–delay product , serial binary adder , digital signal processing , very large scale integration , arithmetic , power (physics) , propagation delay , electronic engineering , computer hardware , mathematics , embedded system , telecommunications , engineering , physics , quantum mechanics , latency (audio) , computer network
Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.