Open AccessPOWER REDUCTION BY GUARDED EVALUATION CONSIDERING LOGIC ARCHITECTURE AND USING CLOCK GATING
Author(s) -
G. Suresh,
Amit Kumar
Publication year - 2015
Publication title -
international journal of electrical and electronics engineering
Language(s) - English
Resource type - Journals
ISSN - 2231-5284
DOI - 10.47893/ijeee.2015.1161
Subject(s) - clock gating , correctness , computer science , reduction (mathematics) , combinational logic , power gating , asynchronous circuit , digital electronics , electronic circuit , constant (computer programming) , dynamic demand , electronic engineering , sequential logic , clock signal , power (physics) , logic gate , synchronous circuit , algorithm , transistor , mathematics , engineering , electrical engineering , voltage , physics , geometry , quantum mechanics , programming language
In this paper, guarded evaluation is a dynamic power reduction technique by identifying sub circuits inputs and kept constant at specific times during circuit operation. In certain condition, some signals within the digital design are not observable at output. So make such signals as guarded (constant). There by reducing the dynamic power. Here we apply this technique for all digital circuits. The problem here is to find conditions under which a sub circuit input can be held constant with disturbing the main circuit functionally (correctness). Here we propose a solution for discovering the gating inputs based on inverting and non-inverting methods. By including “clock gating” we still reduce the dynamic power and leakage power especially for sequential circuits and also used to some small combinational circuits.