VHDL IMPLEMENTATION OF GENETIC ALGORITHM FOR 2-BIT ADDER
Author(s) -
A VEDAVATHI.,
MEENA. K.V,
Gayatri Malhotra
Publication year - 2014
Publication title -
international journal of electronics and electical engineering
Language(s) - English
Resource type - Journals
ISSN - 2231-5284
DOI - 10.47893/ijeee.2014.1120
Subject(s) - evolvable hardware , adder , computer science , vhdl , genetic algorithm , evolutionary algorithm , genetic programming , computer architecture , combinational logic , electronic circuit , computer engineering , logic gate , theoretical computer science , algorithm , field programmable gate array , artificial intelligence , computer hardware , engineering , machine learning , electrical engineering , telecommunications , latency (audio)
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