Open AccessOPTIMAL DESIGN FOR GROUND BOUNCE NOISE REDUCTION USING SLEEP TRANSISTOR
Author(s) -
P. Sreenivasulu,
Vasavi Prasanthi Dasari
Publication year - 2012
Publication title -
international journal of electrical and electronics engineering
Language(s) - English
Resource type - Journals
ISSN - 2231-5284
DOI - 10.47893/ijeee.2012.1022
Subject(s) - ground bounce , noise margin , transistor , electrical engineering , electronic engineering , adder , cmos , noise (video) , flicker noise , phase noise , engineering , noise temperature , noise immunity , leakage (economics) , noise generator , computer science , noise figure , voltage , electronic circuit , field effect transistor , artificial intelligence , image (mathematics) , amplifier , economics , macroeconomics
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been introduced with improved staggered phase damping technique for further reduction in the peak of ground bounce noise. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and ground bounce noise. The simulation results depicts that the proposed design also leads to efficient 1bit full adder cells in terms of standby leakage power, active power, ground bounce noise and noise margin. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.