Open AccessDESIGN OF CONFIGURABLE IP CORE FOR ERROR DETECTION AND CORRECTION
Author(s) -
Ajilesh Rk,
K Anand,
Rajalakshmi Nandakumar
Publication year - 2014
Publication title -
international journal of computer science and informatics
Language(s) - English
Resource type - Journals
ISSN - 2231-5292
DOI - 10.47893/ijcsi.2014.1144
Subject(s) - decoding methods , computer science , error detection and correction , hamming code , word (group theory) , algorithm , encoding (memory) , coding (social sciences) , hamming distance , computer hardware , coding gain , transmission (telecommunications) , arithmetic , block code , mathematics , telecommunications , artificial intelligence , statistics , geometry
This paper addresses the design & implementation of configurable Intellectual Property (IP) core for double error detection and single error Correction. The encoding /decoding algorithms considered in this can be implemented with a simple and faster hardware. The block can be used for coding and decoding word having any length and correct single bit error occurred and detect double bit error, during transmission. The user can define the word length and the hamming bits required.