Open AccessPower Optimization For A Datapath Of General Purpose Processor
Author(s) -
Vijayalakshmi. Nariseti
Publication year - 2011
Publication title -
international journal of computer science and informatics
Language(s) - English
Resource type - Journals
ISSN - 2231-5292
DOI - 10.47893/ijcsi.2011.1012
Subject(s) - datapath , adder , network topology , multiplier (economics) , computer science , computer architecture , implementation , path (computing) , topology (electrical circuits) , parallel computing , electronic engineering , engineering , electrical engineering , telecommunications , computer network , latency (audio) , economics , macroeconomics , programming language
This paper explores different data path architecture topologies for low power solutions. And we look at the energy optimization of different topologies. This paper is aimed at characterizing various architecture implementations of different data path operators like adders and multipliers and a different style of multiplier with minimum power and delay product and different adder topologies.