Feat Of Submerged Scheme Relevance In Power Pc Processor Based Fpga Using Fpga Ip Cores

Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System. This work will also be productive to CSS Division of NSTL in designing and miniaturizing embedded systems such as MCS, MDAC etc. used in marine systems. The present work describes the mellowness of under water system relevance in Power PC Based FPGA using FPGA IP Cores. This work includes understanding the design flow of EDK and learns about various IP Cores Provided by Xilinx EDK 10.1. The underwater system application has been implemented in ‘C’ language by using Xilinx Device Drivers. A custom logic in VHDL has been developed for truncating extra bits of ADC. In Xilinx ISE10.1 project navigator the developed VHDL Code has been integrated with C. The combined bit file generated has been downloaded into Xilinx Virtex-II Pro FPGA Proto Board.