Open AccessFPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder
Author(s) -
J. Tulasi,
T. Venkata Lakshmi,
M. Kamaraju
Publication year - 2016
Publication title -
international journal of computer and communication technology
Language(s) - English
Resource type - Journals
eISSN - 2231-0371
pISSN - 0975-7449
DOI - 10.47893/ijcct.2016.1352
Subject(s) - convolutional code , viterbi decoder , computer science , viterbi algorithm , soft decision decoder , encoder , block code , turbo code , field programmable gate array , serial concatenated convolutional codes , soft output viterbi algorithm , block (permutation group theory) , computer hardware , forward error correction , sequential decoding , real time computing , algorithm , decoding methods , concatenated error correction code , geometry , mathematics , operating system
In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.