z-logo
open-access-imgOpen Access
A NOVEL IMPLEMENTATION OF 32-BIT VLIW-MISC PROCESSOR ON FPGA
Author(s) -
M. Kamaraju,
M. Alekhya,
K. Lal Kishore
Publication year - 2016
Publication title -
international journal of computer and communication technology
Language(s) - English
Resource type - Journals
eISSN - 2231-0371
pISSN - 0975-7449
DOI - 10.47893/ijcct.2016.1339
Subject(s) - very long instruction word , computer science , reduced instruction set computing , compiler , vhdl , instruction level parallelism , field programmable gate array , parallel computing , instruction set , computer architecture , instructions per cycle , parallelism (grammar) , embedded system , computer hardware , central processing unit , programming language

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom