Open AccessMODEL-DRIVEN CLOCK FREQUENCY SCALING FOR CONTROL-DOMINATED EMBEDDED SYSTEMS
Author(s) -
Zdravko Karakehayov
Publication year - 2014
Publication title -
computing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.184
H-Index - 11
eISSN - 2312-5381
pISSN - 1727-6209
DOI - 10.47839/ijc.7.2.516
Subject(s) - computer science , clock rate , frequency scaling , microcontroller , cpu multiplier , embedded system , chip , clock gating , digital clock manager , clock signal , clock domain crossing , power (physics) , computer hardware , synchronous circuit , telecommunications , physics , quantum mechanics , jitter
This paper introduces a combination of models and proofs for optimal power management via clock frequency scaling. The approach is suitable for systems on a chip or microcontrollers where a processor runs in parallel with embedded peripherals. Since the methodology is based on clock rate control, it is very easy to implement. A hardware model, a computational model and an energy model underlie the procedure. We proved that the combination of models is sufficient to determine an optimal clock rate for the CPU. Furthermore, we expand the application space taking into account preemption of tasks. Also, we discuss the role of embedded peripherals when select the clock frequency in both active and power-saving modes. Simulation results manifest the benefits of clock rate control under the proposed methodology. An example shows a 56% increase of the battery lifetime when the clock rate is changed from the lowest possible level to the optimal value.