CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR | Zendy

Xianhong Xu | Zendy; Simon Jones | Zendy

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CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

Author(s) -

Xianhong Xu,

Simon Jones

Publication year - 2014

Publication title -

international journal of computing

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.184

H-Index - 11

eISSN - 2312-5381

pISSN - 1727-6209

DOI - 10.47839/ijc.3.2.279

Subject(s) - computer science , code (set theory) , thumb , rule of thumb , parallel computing , arm architecture , reduced instruction set computing , compression (physics) , software , cache , unreachable code , instruction set , dead code , set (abstract data type) , embedded system , operating system , computer hardware , redundant code , code generation , programming language , key (lock) , medicine , materials science , composite material , anatomy

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

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