Open AccessImplementation and modeling of low power sleepy stack SRAM cell
Author(s) -
Rahul Kakkar,
Sumeet Goyal,
Joginder Singh,
Dishant Khosla,
Sohni Singh
Publication year - 2019
Publication title -
cgc international journal of contemporary technology
Language(s) - English
Resource type - Journals
ISSN - 2582-0486
DOI - 10.46860/cgcijctr.2019.12.20.53
Subject(s) - dissipation , static random access memory , power (physics) , electrical engineering , stack (abstract data type) , electronic engineering , leakage power , low power electronics , backup , leakage (economics) , computer science , engineering , power consumption , physics , transistor , voltage , mechanical engineering , macroeconomics , quantum mechanics , economics , thermodynamics , programming language
for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed.Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current isalso a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell isreduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW withproposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipationthe circuit can have more battery backup and lesser heat emission