Open AccessVLSI IMPLEMENTATION OF HIGH SPEED SINGLE PRECESSION FLOATING POINT UNIT USING VERILOG
Author(s) -
NARAHARI BHARGAVI .,
Babu Rajesh
Publication year - 2022
Publication title -
international journal of engineering technology and management sciences
Language(s) - English
Resource type - Journals
ISSN - 2581-4621
DOI - 10.46647/ijetms.2022.v06i01.003
Subject(s) - operand , floating point , verilog , computer science , subtraction , multiplication (music) , arithmetic , interfacing , ieee floating point , floating point unit , division (mathematics) , computer hardware , double precision floating point format , adder , mathematics , algorithm , field programmable gate array , telecommunications , combinatorics , latency (audio)
Single-precision floating-point format is a computer number format that is used to represent a wide dynamic range of values. Floating point numbers representation has widespread dominance over fixed point numbers. Since the recent years, researchers are putting a lot of efforts in interfacing complex modules which are used in signal processing with processors for increasing the speed. In this work implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, and division functions on 32-bit operands that use the IEEE 754-2008 standard is done using Verilog. The FPU of this work is a single precision IEEE754 compliant integrated unit. Pre-normalization of operands is employed for addition and subtraction, multiplication using bit pair recoding and division using non restoring division. It can handle not only basic floating point operations like addition, subtraction, multiplication and division but can also handle operations like transcendental functions like sine, cosine and tangential function. The logical method for Addition and Subtraction operation is expanded in order to decrease the no. of gates used.