Open AccessDesign of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique
Author(s) -
Pyasa Dileep and A Satyanarayana B Sangeeth Kumar
Publication year - 2020
Publication title -
international journal of modern trends in science and technology
Language(s) - English
Resource type - Journals
ISSN - 2455-3778
DOI - 10.46501/ijmtst060812
Subject(s) - comparator , computer science , spice , realization (probability) , very large scale integration , power (physics) , focus (optics) , electronic engineering , electronic circuit , chip , computer hardware , embedded system , electrical engineering , engineering , mathematics , voltage , telecommunications , statistics , physics , optics , quantum mechanics
In this paper we are design a circuit based on data selector and distributor networks in which we will notrealize the circuit based upon the expressions but off course the circuit which have designed will haveinternally some expression. In the recent trends the need for low power and less on-chip area is on high notefor the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative designof 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDICell as well as selection of primary inputs to the terminals of GDI cell. 8-Bit GDI based Comparator will bedesigned and simulated using Tanner EDATool. Comparator has three main outputs where it can compare theweight of two words and generates three functions. GDI has the advantage of low power consumptionbecause the total number of logic devices needed willbe less and it can also operate with high speed due toaffective realization of logic using minimal hardware. Comparator circuits is designed using tanner tools andalso observe the simulation results in H-SPICE attaining low power and less delay.