Open AccessA Novel Thermal Modeling of Through Silicon Vias in 3-D IC structures
Author(s) -
Chandrashekhar V. Patil
Publication year - 2021
Publication title -
international journal of materials
Language(s) - English
Resource type - Journals
ISSN - 2313-0555
DOI - 10.46300/91018.2020.7.19
Subject(s) - interposer , thermal resistance , heat transfer , planar , through silicon via , thermal , materials science , substrate (aquarium) , integrated circuit , mechanical engineering , realization (probability) , silicon , electronic engineering , computational fluid dynamics , computer science , engineering , optoelectronics , mechanics , aerospace engineering , nanotechnology , physics , geology , oceanography , etching (microfabrication) , computer graphics (images) , statistics , layer (electronics) , mathematics , meteorology
Heat mitigation is a major challenge in 3-D IC (ThreeDimensional Integrated Circuit) realization. A study of the analytical thermal behavior of the TSV (Through Silicon Via) is very important. Simple and compact yet other models were found deficient to solve this problem in the literature survey. In this paper resistance networks are used to model the heat transfer of the TSVs, in both vertical and horizontal directions, in simpler and compact models. The accuracy of such models is compared with commercially available CFD (Computational Fluid Dynamics) tool. The error of corrections between the tool and developed models are corrected by multiplication factors, resulted within 4.18% accuracy. Varying the thicknesses of a liner, filer, soldering and substrate materials are studied concerning heat transfer physical behavior of three planar TSV stacked systems. The major purpose is to incorporate both vertical and horizontal thermal resistance networks captured more accurately in heat dissipated paths. Proposed models of TSVs can be used in the active interposer simulations or in the face2face fabrication stacked methods of the 3-D IC structures.