Open AccessTuning Logic Simulator for Estimation of VLSI Timing Degradation under Aging
Author(s) -
Miljana Milić
Publication year - 2019
Publication title -
advances in electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 23
eISSN - 1844-7600
pISSN - 1582-7445
DOI - 10.4316/aece.2019.03009
Subject(s) - very large scale integration , degradation (telecommunications) , computer science , logic simulation , logic gate , simulation , real time computing , embedded system , parallel computing , computer architecture , algorithm , telecommunications