Open AccessInstruction-level Real-time Secure Processor Using an Error Correction Code
Author(s) -
Se Chang Yoon,
S. W. Lee,
J. K. Park,
J. T. Kim
Publication year - 2015
Publication title -
advances in electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.254
H-Index - 23
eISSN - 1844-7600
pISSN - 1582-7445
DOI - 10.4316/aece.2015.03002
Subject(s) - computer science , code (set theory) , error detection and correction , parallel computing , real time computing , embedded system , programming language , algorithm , set (abstract data type)
In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area