Open AccessCharacteristics of P‐channel SOI LDMOS Transistor with Tapered Field Oxides
Author(s) -
Kim Jongdae,
Kim SangGi,
Roh Tae Moon,
Park Hoon Soo,
Koo JinGun,
Kim Dae Yong
Publication year - 1999
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.99.0199.0304
Subject(s) - ldmos , materials science , breakdown voltage , power mosfet , silicon on insulator , optoelectronics , oxide , transistor , field effect transistor , electrical engineering , field (mathematics) , voltage , mosfet , electronic engineering , silicon , engineering , mathematics , pure mathematics , metallurgy
A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On‐resistance of P‐channel RESURF (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at V gs = −5.0 V , the specific on‐resistance of the LDMOS with the tapered field oxide is about 31.5 mΩ · cm 2 , while that of the LDMOS with the conventional field oxide is about 57 mΩ · cm 2 .