Open AccessDesign and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase‐Locked Loop
Author(s) -
Song Jae Ho,
Yoo Tae Whan,
Ko Jeong Hoon,
Park Chang Soo,
Kim Jae Keun
Publication year - 1999
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.99.0199.0301
Subject(s) - jitter , phase locked loop , electronic engineering , loop (graph theory) , compensation (psychology) , voltage , materials science , computer science , electrical engineering , engineering , mathematics , psychology , combinatorics , psychoanalysis
A clock and data recovery circuit with a phase‐locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri‐correlation architecture is used for frequency‐ and phase‐locked loop. A NRZ‐to‐PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU‐T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp‐p were showed. The temperature compensation characteristics were tested for the operating temperature from −10 to 60 °C and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single‐mode fiber with the length of 400 km and operated successfully.