Open AccessIntegration of 5‐V CMOS and High‐Voltage Devices for Display Driver Applications
Author(s) -
Kim Jongdae,
Park MunYang,
Kang Jin Yeong,
Lee Sangyong,
Koo JinGun,
Nam KeeSoo
Publication year - 1998
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.98.0198.0104
Subject(s) - cmos , materials science , voltage , transistor , electrical engineering , low voltage , optoelectronics , overdrive voltage , fabrication , field emission display , field effect transistor , breakdown voltage , integrated circuit , chip , plasma display , threshold voltage , engineering , field electron emission , electrode , physics , medicine , alternative medicine , pathology , quantum mechanics , electron
Reduced surface field lateral double‐diffused MOS transistors for the driving circuits of plasma display panel and field emission display in the 120 V region have been integrated for the first time into a low‐voltage 1.2 μ m analog CMOS process using p‐type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers and also the cost of fabrication. The lateral double‐diffused MOS transistor with a drift length of 6.0 μ m and a breakdown voltage greater than 150 V was self‐isolated to the low voltage CMOS ICs. The measured specific onresistance of the lateral double‐diffused MOS is 4.8 mΩ·cm 2 at a gate voltage of 5 V.