Open AccessAn Amorphous Silicon Local Interconnection (ASLI) CMOS with Self‐Aligned Source/Drain and Its Electrical Characteristics
Author(s) -
Yoon YongSun,
Baek KyuHa,
Park JongMoon,
Nam KeeSoo
Publication year - 1997
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.97.0197.0406
Subject(s) - pmos logic , materials science , optoelectronics , cmos , drain induced barrier lowering , amorphous silicon , electrical engineering , ring oscillator , depletion region , silicon , interconnection , voltage , threshold voltage , transistor , semiconductor , engineering , crystalline silicon , telecommunications
A CMOS device which has an extended heavily‐doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self‐aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional ones. The electrical characteristics of this device are as good as those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71‐stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3 V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.