Open AccessHigh‐Speed Array Multipliers Based on On‐the‐Fly Conversion
Author(s) -
Moh SangMan,
Yoon SukHan
Publication year - 1997
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.97.0197.0401
Subject(s) - adder , multiplication (music) , on the fly , multiplier (economics) , computer science , arithmetic , electronic engineering , computer hardware , parallel computing , mathematics , engineering , cmos , combinatorics , economics , macroeconomics , operating system
A new on‐the‐fly conversion algorithm is proposed, and high‐speed array multipliers with the on‐the‐fly conversion are presented. The new on‐the‐fly conversion logic is used to speed up carry‐propagate addition at the last stage of multiplication, and provides constant delay independent of the number of input bits. In this paper, the multiplication architecture and the on‐the‐fly conversion algorithm are presented and discussed in detail. The proposed architecture has multiplication time of ( n + 1) t FA , where n is the number of input bits and t FA is the delay of a full adder. According to our comparative performance evaluation, the proposed architecture has shorter delay and requires less area than the conventional array multiplier with on‐the‐fly conversion.