Open AccessAB9: A neural processor for inference acceleration
Author(s) -
Cho Yong Cheol Peter,
Chung Jaehoon,
Yang Jeongmin,
Lyuh ChunGi,
Kim HyunMi,
Kim Chan,
Ham Jeseok,
Choi Minseok,
Shin Kyoungseon,
Han Jinho,
Kwon Youngsu
Publication year - 2020
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.2020-0134
Subject(s) - computer science , acceleration , static random access memory , artificial neural network , graphics , multi core processor , chip , graphics processing unit , process (computing) , parallel computing , embedded system , computer hardware , artificial intelligence , operating system , telecommunications , physics , classical mechanics
We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on‐chip memory. Complementing the hardware is an intuitive and user‐friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40‐TFLOP STC that includes 32k arithmetic units and over 36 MB of on‐chip SRAM, our baseline implementation of AB9 consists of a 1‐GHz quad‐core setup with other various industry‐standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general‐purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28‐nm process with a chip size of 17 × 23 mm 2 . Delivery is expected later this year.