Open AccessFunction‐level module sharing techniques in high‐level synthesis
Author(s) -
Nishikawa Hiroki,
Shirane Kenta,
Nozaki Ryohei,
Taniguchi Ittetsu,
Tomiyama Hiroyuki
Publication year - 2020
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.2020-0107
Subject(s) - high level synthesis , computer science , redundancy (engineering) , reuse , register transfer level , computer architecture , function (biology) , shared resource , high level design , embedded system , field programmable gate array , logic synthesis , engineering , algorithm , logic gate , scheduling (production processes) , operating system , operations management , evolutionary biology , iterative design , biology , waste management
High‐level synthesis (HLS), which automatically synthesizes a register‐transfer level (RTL) circuit from a behavioral description written in a high‐level programming language such as C/C++, is becoming a more popular technique for improving design productivity. In general, HLS tools often generate a circuit with a larger area than those of hand‐designed ones. One reason for this issue is that HLS tools often generate multiple instances of the same module from a function. To eliminate such a redundancy in circuit area in HLS, HLS tools are capable of sharing modules. Function‐level module sharing at a behavioral description written in a high‐level programming language may promote function reuse to increase effectiveness and reduce circuit area. In this paper, we present two HLS techniques for module sharing at the function level.