Open AccessLow energy and area efficient quaternary multiplier with carbon nanotube field effect transistors
Author(s) -
Rahmati Saeed,
Farshidi Ebrahim,
Ganji Jabbar
Publication year - 2021
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.2020-0045
Subject(s) - carbon nanotube field effect transistor , adder , multiplier (economics) , multiplexer , spice , electronic engineering , electronic circuit , transistor , serial binary adder , computer science , field effect transistor , engineering , electrical engineering , voltage , cmos , multiplexing , economics , macroeconomics
In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field‐effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best‐performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.