Open AccessCMOS true‐time delay IC for wideband phased‐array antenna
Author(s) -
Kim Jinhyun,
Park Jeongsoo,
Kim JeongGeun
Publication year - 2018
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.2018-0113
Subject(s) - attenuator (electronics) , wideband , true time delay , cmos , phased array , return loss , electrical engineering , amplifier , electronic engineering , physics , materials science , antenna (radio) , engineering , attenuation , optics
This paper presents a true‐time delay ( TTD ) using a commercial 0.13‐μm CMOS process for wideband phased‐array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers ( WDGA s), a 7‐bit TTD circuit, and a 6‐bit digital step attenuator ( DSA ) circuit. The T‐type attenuator with a low‐pass filter and the WDGA s are implemented for a low insertion loss error between the reference and time‐delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB , respectively, at 2 GHz–18 GHz. The maximum time delay of 198 ps with a 1.56‐ps step and the maximum attenuation of 31.5 dB with a 0.5‐ dB step are achieved at 2 GHz–18 GHz. The RMS time‐delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz–18 GHz. An output P1 dB of <−0.5 dBm is achieved at 2 GHz–18 GH z. The chip size is 3.3 × 1.6 mm 2 , including pads, and the DC power consumption is 370 mW for a 3.3‐V supply voltage.