Open AccessDesign of Multi‐time Programmable Memory for PMICs
Author(s) -
Kim YoonKyu,
Kim MinSung,
Park Heon,
Ha ManYeong,
Lee JungHwan,
Ha PanBong,
Kim YoungHee
Publication year - 2015
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.15.0114.1428
Subject(s) - transistor , sense amplifier , sense (electronics) , memory cell , voltage , electrical engineering , capacitor , computer science , static induction transistor , non volatile memory , threshold voltage , electronic engineering , engineering
In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of 1 rows × 64 columns and a user memory area of 3 rows × 64 columns , is newly proposed in this paper.