Open AccessDesign and Implementation of 256‐Point Radix‐4 100 Gbit/s FFT Algorithm into FPGA for High‐Speed Applications
Author(s) -
Polat Gokhan,
Ozturk Sitki,
Yakut Mehmet
Publication year - 2015
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.15.0114.0678
Subject(s) - fast fourier transform , radix (gastropod) , field programmable gate array , gigabit , computer science , point (geometry) , computer hardware , algorithm , mathematics , telecommunications , botany , biology , geometry
The third‐party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256‐point Radix‐4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high‐speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix‐4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex‐6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.