Open AccessProgram Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications
Author(s) -
Park SeChun,
Kim YouSung,
Cho HoYoub,
Choi SungDae,
Yoon MiSun,
Kim TaeYun,
Park KunWoo,
Park Jongsun,
Kim SooWon
Publication year - 2014
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.14.0213.0537
Subject(s) - cache , smart cache , page cache , cache invalidation , cache pollution , computer science , cache coloring , write buffer , flash (photography) , nand gate , cache algorithms , computer hardware , cpu cache , parallel computing , logic gate , algorithm , physics , optics
In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.