Robust Two‐Phase Clock Oxide TFT Shift Register over Threshold Voltage Variation and Clock Coupling Noises

This letter describes a two‐phase clock oxide thin‐film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART‐SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from −4 V to 5 V at a line time of 5 μs. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively −12.6 dB and −26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16‐stage shift registers atV T H = − 1.56   V , compared to 11.5 mW for the conventional circuits.