Open AccessRobust Two‐Phase Clock Oxide TFT Shift Register over Threshold Voltage Variation and Clock Coupling Noises
Author(s) -
Nam Hyoungsik,
Song Eunji
Publication year - 2014
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.14.0213.0228
Subject(s) - clock skew , shift register , coupling (piping) , threshold voltage , clock signal , transistor , node (physics) , voltage , electronic engineering , electrical engineering , materials science , physics , electronic circuit , computer science , optoelectronics , engineering , acoustics , metallurgy
This letter describes a two‐phase clock oxide thin‐film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART‐SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from −4 V to 5 V at a line time of 5 μs. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively −12.6 dB and −26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16‐stage shift registers atV T H = − 1.56 V , compared to 11.5 mW for the conventional circuits.