Open AccessVoltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs
Author(s) -
Jang Cheoljon,
Chong Jongwha
Publication year - 2014
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.14.0113.1233
Subject(s) - three dimensional integrated circuit , power network design , interconnection , voltage , voltage drop , power (physics) , stacking , electronic engineering , power integrity , chip , through silicon via , engineering , electrical engineering , signal integrity , telecommunications , physics , quantum mechanics , wafer , nuclear magnetic resonance
To reduce interconnect delay and power consumption while improving chip performance, a three‐dimensional integrated circuit (3D IC) has been developed with die‐stacking and through‐silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR‐drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR‐drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR‐drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.