Open Access10‐Bit 200‐MS/s Current‐Steering DAC Using Data‐Dependant Current‐Cell Clock‐Gating
Author(s) -
Yang ByungDo,
Seo BoSeok
Publication year - 2013
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.13.0212.0286
Subject(s) - spurious free dynamic range , signal (programming language) , cmos , power (physics) , digital to analog converter , 12 bit , electrical engineering , clock rate , sampling (signal processing) , electronic engineering , clock signal , bit (key) , voltage , physics , computer science , engineering , electronic circuit , filter (signal processing) , quantum mechanics , programming language , computer security
This letter proposes a low‐power current‐steering digital‐to‐analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current‐source cells in which the data will not be changed. The 10‐bit DAC is implemented using a 0.13‐μm CMOS process with V DD =1.2 V. Its area is 0.21 mm 2 . It consumes 4.46 mW at a 1‐MHz signal frequency and 200‐MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25‐MHz and 10‐MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1‐MHz and 50‐MHz signal frequencies, respectively.