Open AccessArchitectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL
Author(s) -
Oh MyeongHoon,
Kim Young Woo,
Kwak Sanghoon,
Shin ChiHoon,
Kim SungNam
Publication year - 2013
Publication title -
etri journal
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.295
H-Index - 46
eISSN - 2233-7326
pISSN - 1225-6463
DOI - 10.4218/etrij.13.0112.0598
Subject(s) - asynchronous communication , computer science , asynchronous circuit , cmos , computer architecture , microarchitecture , asynchronous system , power consumption , power (physics) , processor design , electronic engineering , embedded system , parallel computing , computer hardware , synchronous circuit , clock signal , engineering , telecommunications , physics , quantum mechanics , jitter
As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.